This invention relates to a field-effect transistor load circuit, and more particularly to a metal semiconductor field-effect transistor load circuit, for a circuit such as a gallium-arsenide integrated logic circuit or for the bit line of a gallium-arsenide integrated memory circuit.
Hereinafter a field-effect transistor will be referred to as an FET and a metal semiconductor field-effect transistor as an MESFET. The source electrode gate electrode, and drain electrode of an FET will be referred to as simply the source gate, and drain. An enhancement-mode FET, that is an FET which is normally in the off state, will be denoted an EFET. A depletion-mode FET, that is, an FET which is normally in the on state, will be denoted a DFET. The symbol Vdd will denote the supply voltage of the circuit under discussion, and Vss will denote the ground potential of 0V.
Due to their high operating speeds, integrated galliumarsenide logic and memory devices are coming into use in cache memories and peripheral logic devices for high-speed microprocessors, and in other digital applications in which speed is a critical factor. A circuit design that has been widely employed in these applications is the direct-coupled FET logic (DCFL) design described for example in the first edition of Kagobutsu Handotai Debaisu II (Compound Semiconductor Devices II) by Imai, Ikoma, Sato, and Fujimoto, published by Kogyo Chosakai on Jan. 10, 1985, pages 6 to 9, and illustrated in FIG. 1.
The device in FIG. 1 is an inverter logic circuit comprising an input terminal Vin 1, an output terminal Vout 2, and an EFET 3 that receives an input signal Vin from the input terminal 1 at its gate and provides the inverted signal from its source to the output terminal 2. The prior-art load circuit 10 connected to this logic circuit comprises a DFET 11, the gate and source electrodes of which are electrically coupled to each other and to the drain of the EFET 3. The drain of the EFET 3 and source of the DFET 11 are also coupled to Vss through a Schottky diode 20 that is present between the gate and channel of the next-stage logic transistor. This diode will hereinafter be referred to as a parasitic diode. The drain of the DFET 11 is connected to Vdd; the source of the EFET 3 is connected to Vss. The interconnection between the source and gate of the DFET 11 assures that the DFET 11 is always in the on state, permitting load current to flow.
The operating characteristics of this circuit are illustrated in FIG. 2, which shows the relationship between the load current 1 and the output signal voltage Vout. In FIG. 2. L denotes the load curve of the load circuit 10 in FIG. 1. Cl denotes the characteristic curve of the EFET 3 when the input signal Vin denotes at the High logic level. Ch is the characteristic curve of the EFET 3 when the input signal Vin denotes at the Low logic level, and Cd is the forward characteristic curve of the parasitic diode 20 in the next stage. When the input signal Vin is High, the circuit operates at the point of intersection Pl of the L and Cl curves, and the output signal Vout is at the Low potential V1, which is approximately 0.1V. When the input signal Vin changes from High to Low, the characteristic curve of the EFET 3 changes from Cl to Ch. If the output terminal Vout 2 were unconnected, the circuit would operate at the point Pha and the output voltage Vout would be close to Vdd. Because the circuit is connected to a next-stage DCFL logic circuit, however the output voltage cannot rise substantially above the forward turn-on voltage Vf of the next-stage parasitic diode 20, which thus clamps the output signal Vout to a value of approximately 0.6V to 0.8V. This accordingly becomes the High output logic level Vh, and the circuit operates at the point Ph. In the region between the Low and High output logic levels, the load DFET 11 saturates and operates as a constant-current source so the current flowing through the load circuit is clamped to a substantially constant value Icr.
The comparatively small DCFL logic swing of 0.5V to 0.7V and the extremely high electron mobility of gallium arsenide combine to enable circuits of the type illustrated in FIG. 1 to operate at high speeds. A problem is present with the circuit shown in FIG. 1, however, in that the relatively high current times voltage product at the point Ph causes an unnecessary amount of power to be dissipated in the High output state. A further problem is present in that if a load DFET 11 with a large current gain coefficient .beta. is employed to increase the driving power of the circuit the resulting large inflow of clamp current to the gate of the next-stage EFET creates a large voltage effect in the source resistance of this EFET. which raises the Low logic level of the next-stage circuit. Since the logic swing of the circuit is only 0.5V to 0.7V to begin with, elevation of the Low logic level seriously reduces the operating margin of the circuit and can lead to instability.